1. Field of the Invention
The invention relates generally to semiconductor devices for operation processings, and more particularly to a semiconductor device which executes inference involving ambiguity, that is, fuzzy inference.
2. Description of the Background Art
In recent years, a system which treats ambiguity in terms such as "large" or "fast" has been put into practical use. When a fuzzy theory is applied to a system, fuzzy inference is executed.
A typical method of fuzzy inference includes steps of adding results of fuzzy rules in accordance with degrees at which the individual fuzzy rules are satisfied (max-min operation), calculating the center of gravity of a result of the combination of the rules (defuzzifier) and determining the center of gravity as a conclusion of the fuzzy inference.
A fuzzy rule defines a relationship, for example, between input values A and B and an output value X in such a form as "if A=BIG and B=NORMAL, then X=SMALL". In fuzzy inference, a certain input value is converted into a value within the range of 0 through 1 for a subsequent operation. Such conversion is defined by a membership function. A membership function represents a fuzzy set and is defined for each proposition with which a fuzzy rule deals (for example, for "large", "normal" or "small").
FIG. 1 illustrates a most popular method of fuzzy inference in a case of two fuzzy rules and two input values and one output value. Referring to FIG. 1, a fuzzy rule 1 has a membership function m1a(a) which is defined with respect to an input value, a. A membership value m1a(a0) with respect to an input value a0 is calculated by substituting the input value a0 into the membership function m1a(a). Also with respect to the output value x, a membership function m1x(x) is defined.
A fuzzy set with respect to an input value, a, (provided by a membership function m1a(a)) is called a condition portion while a fuzzy set with respect to an output value x (provided by a membership function m1x(x)) is called a conclusion portion. The fuzzy rule 1 describes a rule that "if a=m1a(1), then x=m1x(1)".
Also in another fuzzy rule 2, a membership function m2a(a) is defined with respect to an input value, a, while another membership function m2b(b) is defined with respect to an input value b. Further, in the conclusion portion of the fuzzy rule 2, a membership function m2x(x) is defined with respect to an output value, x.
The fuzzy rule 2 describes a rule having two inputs and one output and thus describes a proposition that "if a=m2a(1) and b=m2b(1), then x=m2x(1)".
Generally, a fuzzy inference system includes a plurality of fuzzy rules and provides a plurality of output values because it provides output values from the respective rules with respect to a plurality of input values. A method of fuzzy inference will be described with reference to FIG. 1.
It is assumed that, in the system represented by the fuzzy set of FIG. 1, input values a0 and b0 are provided as input variables a and b. At the condition portion of the fuzzy rule 1, a membership value m1a(a0) is calculated in accordance with the membership function m1a(a). At the condition portion of the fuzzy rule 2, membership values m2a(a0) and m2b(b0) are calculated in accordance with the membership functions m2a(a) and m2b(b). Consequently, degrees at which the individual input values satisfy the respective conditions are calculated.
In order to determine the degrees at which the input values a0 and b0 satisfy the rules, a minimum value among membership values is found out for each of the rules. Such calculation is called a MIN operation. As seen from FIG. 1, m1a(a0) is a minimum value in the rule 1 while m2b(b0) is a minimum value in the rule 2.
A fuzzy set of the conclusion portion of each of the rules is limited using a minimum value among membership values found out for each of the rules. In the rule 1, the membership function m1x(x) of the conclusion portion is cut away by m1a(a0), and in the rule 2, the membership function m2x(x) of the conclusion portion is cut away by the minimum value m2b(b0). The remaining portions of the membership functions at the conclusion portions (indicated by hatched areas in FIG. 1) are denoted by m1x'(x) and m2x'(x), respectively.
Subsequently, in order to compare membership values corresponding to output values x of the conclusion portions for the rules to obtain a maximum value between them to form a new membership function, the membership functions m1x'(x) and m2x'(x) are ORed. Such calculation to determine a maximum value is called a MAX operation. A function obtained by such OR operation is assumed as a membership function mx(x) with respect to the output variable x.
Generally, a value x0 of the center of gravity of the membership function mx(x) is calculated according to the relation of ##EQU1## , and the value x0 of the center of gravity is used as a final output value for the output x, that is, as a result of the inference. The foregoing is the most popular method of fuzzy inference.
Fuzzy inference can be executed by a series of calculations including (1) a calculation of membership values, (2) a calculation of minimum values (MIN operation), (3) a calculation of a maximum value (MAX operation) and (4) a calculation of the center of gravity. When such fuzzy inference is to be executed by software, it is necessary to execute calculations for each of rules. More specifically, a calculation of membership values and a MIN operation are executed for each rule. After such calculations are executed for all of the rules, a MAX operation must be executed for all of the final results. Consequently, in fuzzy inference depending upon software, the processing speed is decreased in proportion to the number of rules.
Various fuzzy inference executing devices on hardware have been proposed in which different rules are processed in a parallel relationship in order to increase the processing speed.
FIG. 2 shows an example of construction of a conventional semiconductor chip which executes fuzzy inference disclosed, for example, in Nikkei Electronics, No. 426, Jul. 27, 1987, P. 150. The fuzzy inference chip shown in FIG. 2 can realize a fuzzy inference system for 16 rules, 4 input variables (at a maximum) and 2 output variables (at a maximum). Input variables and output variables normally are fuzzy sets.
Referring to FIG. 2, the fuzzy inference chip includes four memories 2-1, 2-2, 2-3 and 2-4 for storing therein membership functions for 16 rules with respect to respective input variables a, b, c and d which are received by way of input signal lines 1-1, 1-2, 1-3 and 1-4, respectively. Each of the input signal lines 1-1 to 1- 4 has a width of 4 bits.
The conventional fuzzy inference chip further includes 16 minimum (min) operation circuits 103-1 to 103-16 each of which receives membership values of corresponding rules from the memories 2-1 to 2-4 and determines a minimum one of the membership values in order to find out a minimum membership value for each of the 16 rules.
The fuzzy inference chip further includes, in order to provide a construction of a conclusion portion of fuzzy inference, a memory 4 in which membership functions for 16 individual rules with respect to an output variable x are stored, another memory 5 in which membership functions for the 16 individual rules with respect to another output variable y are stored, and comparator circuits 6-1 to 6-16 and 7-1 to 7-16 for cutting away membership functions for 16 rules with respect to each of the output variables x and y, with minimum membership values for the individual rules. The comparator circuits 6-1 to 6-16 receive and compare respective outputs of the min operation circuits 103-1 to 103-16 with corresponding outputs of the memory 4. The other comparator circuits 7-1 to 7-16 compare respective outputs of the memory 5 and corresponding outputs of the min operation circuits 103-1 to 103-16.
The conventional fuzzy inference chip further includes a max operation circuit 8 for receiving outputs of the comparator circuits 6-1 to 6-16 and determining a maximum value among them, another max operation circuit 9 for receiving outputs of the comparator circuits 7-1 to 7-16 and determining a maximum value among them, a gravity center calculating circuit 10 for calculating the center of gravity of a membership function for the output x from an output of the max operation circuit 8, and another gravity center calculating circuit 11 for determining the center of gravity of a membership function for the output y from an output of the max calculating circuit 9. An output of the gravity center calculating 10 is transmitted by way of an output signal line 12 having a width of 6 bits and provides an inference result x0 with respect to the output variable x. An output of the other gravity center calculating circuit 11 is transmitted by way of another output signal line 13 having a width of 6 bits and provides an inference result y0 with respect to the output variable y. Operation of the conventional fuzzy inference chip will be described subsequently, with reference to FIG. 3 which is an operation flow diagram of the fuzzy chip.
Each of the memories 2-1 to 2-4 has membership functions stored therein which represent fuzzy sets for the 16 rules with respect to a corresponding one of the input variables a to d. Similarly, the memories 4 and 5 have membership functions stored therein which represent fuzzy sets for the 16 rules with respect to the output variables x and y, respectively. Each of the memories 2-1 to 2-4 has addresses designated by one of either an input variable or output variable of 4 bits and stores a corresponding binary membership value of 4 bits in each address thereof. Accordingly, each of the input variables, output variables and membership values is processed with a degree of accuracy of 16 levels (4 bits).
If input values (a, b, c, d) are given in this condition, then the fuzzy inference chip executes inference. For example, if input data, a, of 4 bits are provided to the memory 2-1 by way of the input signal line 1-1, then the memory 2-1 outputs 16 data each of 4 bits representative of each of 16 membership values for the 16 rules. The 16 data of 4 bits from the memory 2-1 are individually provided to the min operation circuits 103-1 to 103-16 provided correspondingly for the 16 individual rules. Similarly, input values b, c and d are provided to the memories 2-2 to 2-4 by way of the input signal lines 1-2 to 1-4, respectively, and 16 membership values are outputted from each of the memories 1-2 to 1-4 and provided to the min operation circuits 103-1 to 103-16 (step S1).
Each of the min operation circuits 103-1 to 103-16 determines a minimum value among the four 4-bit data representative of four membership values received from the memories 2-1 to 2-4. Consequently, a minimum membership value for each of the 16 rules is determined. Outputs of the individual min operation circuits 103-1 to 103-16 are transmitted to corresponding ones of the comparator circuits 6-1 to 6-16 and 7-1 to 7-16 provided for the individual rules (step S2).
Memories 4 and 5 have membership values for outputs xi and yi read out sequentially to be supplied to the circuits 6-1 to 6-16 and 7-1 to 7-16 (step S3).
Each of the comparator circuits 6-1 to 6-16 compares a membership value from a corresponding one of the min operation circuits with a corresponding membership value from the memory 4 and passes a smaller one of the two membership values therethrough so that it may be supplied to the max operation circuit 8. Similarly, each of the comparator circuits 7-1 to 7-16 compares a membership value from a corresponding one of the min operation circuits and a corresponding membership value from the memory 5 and passes a smaller one of the two membership values so that it may be supplied to the max operation circuit 9 (step S4). The processing operations correspond to the operations of determining the hatched areas of the membership functions of the conclusion portions in FIG. 1.
The max operation circuits 8 and 9 determine, for the output variable x and y, a maximum value among membership values from the comparator circuits 6-1 to 6-16 and 7-1 to 7-16 corresponding to the 16 individual rules and transmit the thus determined maximum value to the gravity center calculating circuit 10 and 11, respectively (step S5). This processing operations correspond to the operations of ORing of the cut out membership functions of the conclusion portions in FIG. 1.
The gravity center calculating circuits 10 (or 11) determines the center of gravity for the output variable x (or y) from maximum values supplied thereto for the output variable x (or y) according to the relation ##EQU2## , where mx(xi) is the output of the max operation circuit 8 for the output xi, and outputs the thus determined center of gravity as a result x0 (or y0) of the inference by way of the signal line 12 (or 13) (step S6).
Since the conventional fuzzy inference chip described above can process different rules in a parallel relationship, it can execute fuzzy inference at a higher speed than in software processing. However, in order for such conventional fuzzy inference chip to execute a MIN operation, a MAX operation and an operation for cutting away a membership function for an output variable in a conclusion portion with a minimum membership value, it is necessary for the fuzzy inference chip to make a comparison in magnitude between membership values represented in binary numbers (binary digital values of a 4-bit notation in the example shown in FIG. 1). Since such comparison in magnitude must necessarily proceed successively for individual bits of membership values beginning with the most significant bit, there is a problem in that it is difficult to make such comparison at a high speed.
Further, with the conventional fuzzy inference chip, since hardware is provided fixedly on a semiconductor chip, the number of rules, the number of input variables, the number of output variables and so on are limited by the limitation on hardware, and there is another problem in that the degree of freedom in inference is very low.
Besides, since the conventional fuzzy inference chip is required to include minimum operation circuits and comparator circuits for individual rules, there is a further problem that the configuration of the device is great in size and complicated.
General review and practical applications of fuzzy inference chips are disclosed in Nikkei Electronics, No. 453, Oct. 3, 1988, pp. 157 to 168.